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1 of 17 011101 features real time clock counts seconds, minutes, hours, date of the month, month, day of the week, and year with leap year compensation valid up to 2100 96-byte nonvolatile ram for data storage two time of day alarms - programmable on combination of seconds, minutes, hours, and day of the week 1 hz and 32.768 khz clock outputs serial interface supports motorola serial peripheral interface (spi) serial data ports or standard 3-wire interface burst mode for reading/writing successive addresses in clock/ram dual power supply pins for primary and backup power supplies optional trickle charge output to backup supply 2.0 - 5.5v operation optional industrial temperature range -40c to +85c available in space-efficient 20-pin tssop package recognized by underwriters laboratory ordering information ds1306 16-pin dip DS1306N 16-pin dip (industrial) ds1306e 20-pin tssop ds1306en 20-pin tssop (industrial) pin assignment package dimension information can be found at: http://www.dalsemi.com/datasheets/mechdwg.html pin description v cc1 ? primary power supply v cc2 ? backup power supply v bat ? +3v battery input v ccif ? interface logic power supply input gnd ? ground x1, x2 ? 32.768 khz crystal connection int0 ? interrupt 0 output int1 ? interrupt 1 output sdi ? serial data in sdo ? serial data out ce ? chip enable sclk ? serial clock sermode ? serial interface mode 1 hz - 1 hz output 32 khz - 32.768 khz output ds1306 serial alarm real time clock (rtc) www.dalsemi.com ds1306 20-pin tssop (4.4mm) v cc2 v bat x1 nc x2 nc int0 int1 1 hz gnd v cc1 nc 32 khz v ccif sdo sdi sclk nc ce sermode 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 v cc2 ds1306 16-pin dip (300 mil) 15 x1 int0 1 hz gnd v cc1 sdo sdi sclk ce sermode 1 2 3 4 5 6 7 8 16 14 13 12 11 10 9 v bat x2 int1 32 khz v ccif
ds1306 2 of 17 description the ds1306 serial alarm real time clock provides a full bcd clock calendar which is accessed via a simple serial interface. the clock/calendar provides seconds, minutes, hours, day, date, month, and year information. the end of the month date is automatically adjusted for months with less than 31 days, including corrections for leap year. the clock operates in either the 24-hour or 12-hour format with am/pm indicator. in addition 96 bytes of nonvolatile ram are provided for data storage. an interface logic power supply input pin (v ccif ) allows the ds1306 to drive sdo and 32 khz pins to a level that is compatible with the interface logic. this allows an easy interface to 3-volt logic in mixed supply systems. the ds1306 offers dual power supplies as well as a battery-input pin. the dual power supplies support a programmable trickle charge circuit which allows a rechargeable energy source (such as a super cap or rechargeable battery) to be used for a backup supply. the v bat pin allows the device to be backed up by a non-rechargeable battery. the ds1306 is fully operational from 2.0 to 5.5 volts. two programmable time of day alarms are provided by the ds1306. each alarm can generate an interrupt on a programmable combination of seconds, minutes, hours, and day. ?don?t care? states can be inserted into one or more fields if it is desired for them to be ignored for the alarm condition. a 1 hz and a 32 khz clock output are also available. the ds1306 supports a direct interface to motorola spi serial data ports or standard 3-wire interface. an easy-to-use address and data format is implemented in which data transfers can occur 1 byte at a time or in multiple-byte burst mode. operation the block diagram in figure 1 shows the main elements of the serial alarm rtc. the following paragraphs describe the function of each pin. ds1306 block diagram figure 1
ds1306 3 of 17 signal descriptions v cc1 - dc power is provided to the device on this pin. v cc1 is the primary power supply. v cc2 - this is the secondary power supply pin. in systems using the trickle charger, the rechargeable energy source is connected to this pin. v bat - battery input for any standard 3-volt lithium cell or other energy source. v ccif (interface logic power supply input) - the v ccif pin allows the ds1306 to drive sdo and 32 khz output pins to a level that is compatible with the interface logic, thus allowing an easy interface to 3-volt logic in mixed supply systems. this pin is physically connected to the source connection of the p-channel transistors in the output buffers of the sdo and 32 khz pins. sermode (serial interface mode input) - the sermode pin offers the flexibility to choose between two serial interface modes. when connected to gnd, standard 3-wire communication is selected. when connected to v cc , motorola spi communication is selected. sclk (serial clock input) - sclk is used to synchronize data movement on the serial interface for either the spi or 3-wire interface. sdi (serial data input) - when spi communication is selected, the sdi pin is the serial data input for the spi bus. when 3-wire communication is selected, this pin must be tied to the sdo pin (the sdi and sdo pins function as a single i/o pin when tied together). sdo (serial data output) - when spi communication is selected, the sdo pin is the serial data output for the spi bus. when 3-wire communication is selected, this pin must be tied to the sdi pin (the sdi and sdo pins function as a single i/o pin when tied together). v ccif provides the logic high level. ce (chip enable) - the chip enable signal must be asserted high during a read or a write for both 3-wire and spi communication. this pin has an internal 55k pull-down resistor (typical). int0 (interrupt 0 output) - the int0 pin is an active low output of the ds1306 that can be used as an interrupt input to a processor. the int0 pin can be programmed to be asserted by alarm 0. the int0 pin remains low as long as the status bit causing the interrupt is present and the corresponding interrupt enable bit is set. the int0 pin operates when the ds1306 is powered by v cc1 , v cc2 , or v bat . the int0 pin is an open drain output and requires an external pullup resistor. 1 hz (1 hz clock output) - the 1 hz pin provides a 1 hz squarewave output. this output is active when the 1 hz bit in the control register is a logic 1. both int0 and 1 hz pins are open drain outputs. the interrupt, 1 hz signal, and the internal clock continue to run regardless of the level of v cc (as long as a power source is present). int1 (interrupt 1 output) - the int1 pin is an active high output of the ds1306 that can be used as an interrupt input to a processor. the int1 pin can be programmed to be asserted by alarm 1. when an alarm condition is present, the int1 pin generates a 62.5 ms active high pulse. the int1 pin operates only when the ds1306 is powered by v cc2 or v bat . when active, the int1 pin is internally pulled up to v cc2 or v bat . when inactive, the int1 pin is internally pulled low.
ds1306 4 of 17 32 khz (32.768 khz clock output) - the 32 khz pin provides a 32.768 khz output. this signal is always present. v ccif provides the logic high level. x1, x2 - connections for a standard 32.768 khz quartz crystal. the internal oscillator is designed for operation with a crystal having a specified load capacitance of 6 pf. for more information on crystal selection and crystal layout considerations, please consult application note 58, ?crystal considerations with dallas real time clocks.? the ds1306 can also be driven by an external 32.768 khz oscillator. in this configuration, the x1 pin is connected to the external oscillator signal and the x2 pin is floated. clock, calendar, and alarm the time and calendar information is obtained by reading the appropriate register bytes. the real time clock registers are illustrated in figure 2. the time, calendar, and alarm are set or initialized by writing the appropriate register bytes. note that some bits are set to 0. these bits will always read 0 regardless of how they are written. also note that registers 12h to 1 fh (read) and registers 92h to 9 fh are reserved. these registers will always read 0 regardless of how they are written. the contents of the time, calendar, and alarm registers are in the binary-coded decimal (bcd) format. rtc registers and address map figure 2 hex address read write bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 range 00h 80h 0 10 sec sec 00-59 01h 81h 0 10 min min 00-59 12 10 01-12 + p/a 02h 82h 0 24 p/a 10 hr hours 00-23 03h 83h 0 0 0 0 0 day 01-07 04h 84h 0 0 10 date date 1-31 05h 85h 0 0 10 month month 01-12 06h 86h 10 year year 00-99 07h 87h m 10 sec alarm 0 sec alarm 0 00-59 08h 88h m 10 min alarm 0 min alarm 0 00-59 12 10 01-12 + p/a 09h 89h m 24 p/a 10 hr hour alarm 0 00-23 0ah 8ah m 0 0 0 0 day alarm 0 01-07 0bh 8bh m 10 sec alarm 1 sec alarm 1 00-59 0ch 8ch m 10 min alarm 1 min alarm 1 00-59 12 10 01-12 + p/a 0dh 8dh m 24 p/a 10 hr hour alarm 1 00-23 0eh 8eh m 0 0 0 0 day alarm 1 01-07 0fh 8fh control register 10h 90h status register 11h 91h trickle charger register 12-1fh 92-9fh reserved 20-7fh a0-ffh 96-bytes user ram note: range for alarm registers does not include mask?m? bits.
ds1306 5 of 17 the ds1306 can be run in either 12-hour or 24-hour mode. bit 6 of the hours register is defined as the 12- or 24-hour mode select bit. when high, the 12-hour mode is selected. in the 12-hour mode, bit 5 is the am/pm bit with logic high being pm. in the 24-hour mode, bit 5 is the second 10-hour bit (20-23 hours). the ds1306 contains two time of day alarms. time of day alarm 0 can be set by writing to registers 87h to 8ah. time of day alarm 1 can be set by writing to registers 8 bh to 8 eh. bit 7 of each of the time of day alarm registers are mask bits (table 1). when all of the mask bits are logic 0, a time of day alarm will only occur once per week when the values stored in timekeeping registers 00h to 03h match the values stored in the time of day alarm registers. an alarm will be generated every day when bit 7 of the day alarm register is set to a logic 1. an alarm will be generated every hour when bit 7 of the day and hour alarm registers is set to a logic 1. similarly, an alarm will be generated every minute when bit 7 of the day, hour, and minute alarm registers is set to a logic 1. when bit 7 of the day, hour, minute, and seconds alarm registers is set to a logic 1, an alarm will occur every second. time of day alarm mask bits table 1 alarm register mask bits (bit 7) seconds minutes hours days 1 1 1 1 alarm once per second 0 1 1 1 alarm when seconds match 0 0 1 1 alarm when minutes and seconds match 0 0 0 1 alarm when hours, minutes, and seconds match 0 0 0 0 alarm when day, hours, minutes, and seconds match special purpose registers the ds1306 has three additional registers (control register, status register, and trickle charger register) that control the real time clock, interrupts, and trickle charger. control register (read 0fh, write 8fh) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 wp 0 0 0 1 hz aie1 aie0 wp (write protect) - before any write operation to the clock or ram, this bit must be logic 0. when high, the write protect bit prevents a write operation to any register, including bits 0, 1, and 2 of the control register. upon initial power up, the state of the wp bit is undefined. therefore the wp bit should be cleared before attempting to write to the device. when wp is set, it must be cleared before any other control register bit can be written. 1 hz (1 hz output enable) - this bit controls the 1 hz output. when this bit is a logic 1, the 1 hz output is enabled. when this bit is a logic 0, the 1 hz output is high z. aie0 (alarm interrupt enable 0) - when set to a logic 1, this bit permits the interrupt 0 request flag (irqf0) bit in the status register to assert int0 . when the aie0 bit is set to logic 0, the irqf0 bit does not initiate the int0 signal.
ds1306 6 of 17 aie1 (alarm interrupt enable 1) - when set to a logic 1, this bit permits the interrupt 1 request flag (irqf1) bit in the status register to assert int1. when the aie1 bit is set to logic 0, the irqf1 bit does not initiate an interrupt signal, and the int1 pin is set to a logic 0 state. status register (read 10h) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 000000irqf1irqf0 irqf0 (interrupt 0 request flag) - a logic 1 in the interrupt request flag bit indicates that the current time has matched the alarm 0 registers. if the aie0 bit is also a logic 1, the int0 pin will go low. irqf0 is cleared when any of the alarm 0 registers are read or written. irqf1 (interrupt 1 request flag) - a logic 1 in the interrupt request flag bit indicates that the current time has matched the alarm 1 registers. if the aie1 bit is also a logic 1, the int1 pin will generate a 62.5- ms active high pulse. irqf1 is cleared when any of the alarm 1 registers are read or written. trickle charge register (read 11h, write 91h) this register controls the trickle charge characteristics of the ds1306. the simplified schematic of figure 3 shows the basic components of the trickle charger. the trickle charge select (tcs) bits (bits 4-7) control the selection of the trickle charger. in order to prevent accidental enabling, only a pattern of 1010 will enable the trickle charger. all other patterns will disable the trickle charger. the ds1306 powers up with the trickle charger disabled. the diode select (ds) bits (bits 2-3) select whether one diode or two diodes are connected between v cc1 and v cc2 . if ds is 01, one diode is selected. if ds is 10, two diodes are selected. if ds is 00 or 11, the trickle charger is disabled independently of tcs. the rs bits select the resistor that is connected between v cc1 and v cc2 . the resistor is selected by the resistor select (rs) bits as shown in table 2. programmable trickle charger figure 3
ds1306 7 of 17 trickle charger resistor select table 2 rs bits resistor typical value 00 none none 01 r1 2 k ? 10 r2 4 k ? 11 r3 8 k ? if rs is 00, the trickle charger is disabled independently of tcs. diode and resistor selection is determined by the user according to the maximum current desired for battery or super cap charging. the maximum charging current can be calculated as illustrated in the following example. assume that a system power supply of 5-volts is applied to v cc1 and a super cap is connected to v cc2 . also assume that the trickle charger has been enabled with one diode and resister r1 between v cc1 and v cc2 . the maximum current i max would therefore be calculated as follows: i max = (5.0v - diode drop)/r1 ~ (5.0v - 0.7v)/2 k ? ~ 2.2 ma obviously, as the super cap charges, the voltage drop between v cc1 and v cc2 will decrease and therefore the charge current will decrease. power control power is provided through the v cc1 , v cc2 , and v bat pins. three different power supply configurations are illustrated in figure 4. configuration 1 shows the ds1306 being backed up by a non-rechargeable energy source such as a lithium battery. in this configuration, the system power supply is connected to v cc1 and v cc2 is grounded. when v cc falls below v bat the device switches into a low current battery backup mode. upon power up, the device switches from v bat to v cc when v cc is greater than v bat + 0.2v. the device is write protected whenever it is switched to v bat . configuration 2 illustrates the ds1306 being backed up by a rechargeable energy source. in this case, the v bat pin is grounded, v cc1 is connected to the primary power supply, and v cc2 is connected to the secondary supply (the rechargeable energy source). the ds1306 will operate from the larger of v cc1 or v cc2 . when v cc1 is greater than v cc2 + 0.2 volt (typical), v cc1 will power the ds1306. when v cc1 is less than v cc2 , v cc2 will power the ds1306. the ds1306 does not write-protect itself in this configuration. configuration 3 shows the ds1306 in battery operate mode where the device is powered only by a single battery. in this case, the v cc1 and v bat pins are grounded and the battery is connected to the v cc2 pin. only these three configurations are allowed. unused supply pins must be grounded.
ds1306 8 of 17 power supply configurations for the ds1306 figure 4 configuration 1: backup supply is a non-rechargeable lithium battery configuration 2: backup supply is a rechargeable battery or super capacitor configuration 3: battery operate mode serial interface the ds1306 offers the flexibility to choose between two serial interface modes. the ds1306 can communicate with the spi interface or with a standard 3-wire interface. the interface method used is determined by the sermode pin. when this pin is connected to v cc , spi communication is selected. when this pin is connected to ground, standard 3-wire communication is selected. serial peripheral interface (spi) the serial peripheral interface (spi) is a synchronous bus for address and data transfer and is used when interfacing with the spi bus on specific motorola microcontrollers such as the 68hc05c4 and the 68hc11a8. the spi mode of serial communication is selected by tying the sermode pin to v cc . four pins are used for the spi. the four pins are the sdo (serial data out), sdi (serial data in), ce (chip enable), and sclk (serial clock). the ds1306 is the slave device in an spi application, with the microcontroller being the master. v bat + 0.2v
ds1306 9 of 17 the sdi and sdo pins are the serial data input and output pins for the ds1306, respectively. the ce input is used to initiate and terminate a data transfer. the sclk pin is used to synchronize data movement between the master (microcontroller) and the slave (ds1306) devices. the shift clock (sclk), which is generated by the microcontroller, is active only during address and data transfer to any device on the spi bus. the inactive clock polarity is programmable in some microcontrollers. the ds1306 determines on the clock polarity by sampling sclk when ce becomes active. therefore either sclk polarity can be accommodated. input data (sdi) is latched on the internal strobe edge and output data (sdo) is shifted out on the shift edge (see table 3 and figure 5). there is one clock for each bit transferred. address and data bits are transferred in-groups of eight. function table table 3 mode ce sclk sdi sdo disable reset l input disabled input disabled high z write h cpol=1* cpol=0 data bit latch high z read h cpol=1 cpol=0 x next data bit shift** * cpol is the ?clock polarity? bit that is set in the control register of the microcontroller. ** sdo remains at high z until 8 bits of data are ready to be shifted out during a read. note: cpha bit polarity in the processor (if applicable) may need to be set accordingly. serial clock as a function of microcontroller clock polarity (cpol) figure 5
ds1306 10 of 17 address and data bytes address and data bytes are shifted msb first into the serial data input (sdi) and out of the serial data output (sdo). any transfer requires the address of the byte to specify a write or read to either a rtc or ram location, followed by 1 or more bytes of data. data is transferred out of the sdo for a read operation and into the sdi for a write operation (see figures 6 and 7). spi single-byte write figure 6 spi single-byte read figure 7 * sclk can be either polarity. the address byte is always the first byte entered after ce is driven high. the most significant bit (a7) of this byte determines if a read or write will take place. if a7 is 0, one or more read cycles will occur. if a7 is 1, one or more write cycles will occur. data transfers can occur 1 byte at a time or in multiple-byte burst mode. after ce is driven high an address is written to the ds1306. after the address, 1 or more data bytes can be written or read. for a single-byte transfer 1 byte is read or written and then ce is driven low. for a multiple-byte transfer, however, multiple bytes can be read or written to the ds1306 after the address has been written. each read or write cycle causes the rtc register or ram address to automatically increment. incrementing continues until the device is disabled. when the rtc is selected, the address wraps to 00h after incrementing to 1 fh (during a read) and wraps to 80h after incrementing to 9 fh (during a write). when the ram is selected, the address wraps to 20h after incrementing to 7 fh (during a read) and wraps to a0h after incrementing to ffh (during a write).
ds1306 11 of 17 spi multiple-byte burst transfer figure 8 3-wire interface the 3-wire interface mode operates similar to the spi mode. however, in 3-wire mode there is one i/o instead of separate data in and data out signals. the 3-wire interface consists of the i/o (sdi and sdo pins tied together), ce, and sclk pins. in 3-wire mode, each byte is shifted in lsb first unlike spi mode where each byte is shifted in msb first. as is the case with the spi mode, an address byte is written to the device followed by a single data byte or multiple data bytes. figure 9 illustrates a read and write cycle. in 3-wire mode, data is input on the rising edge of sclk and output on the falling edge of sclk. 3-wire single byte transfer figure 9 single byte read single byte write i/o is sdi and sdo tied together in burst mode, rst rst is kept high and additional sclk cycles are sent until the end of the burst. rst sclk i/o a0 a1 a2 a3 a4 a5 a6 a7 rst sclk i/o d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 a2 a3 a4 a5 a6 a7
ds1306 12 of 17 absolute maximum ratings* voltage on any pin relative to ground -0.5v to +7.0v operating temperature 0 c to 70 c or ?40c to +85c for industrial (ind) storage temperature -55 c to +125 c soldering temperature 260 c for 10 seconds (dip) see ipc/jedec standard j-std-020a for surface mount devices * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (0 c to 70 c or ?40 to +85c) parameter symbol min typ max units notes supply voltage v cc1 , v cc2 v cc1 , v cc2 2.0 5.5 v 1, 8 logic 1 input v ih 2.0 v cc +0.3 v 1 v cc =2.0v -0.3 +0.3 logic 0 input v il v cc =5v -0.3 +0.8 v1 v bat battery voltage v bat 2.0 5.5 v 1 v ccif supply voltage v ccif 2.0 5.5 v 13 dc electrical characteristics (0 c to 70 c or ?40c to +85c; v cc = 2.0 to 5.5v*) parameter symbol min typ max units notes input leakage i li -100 +500 a output leakage i lo -1 1 a v cc =2.0 0.4 logic 0 output v ol v cc =5v 0.4 v2 v ccif =2.0v 1.6 logic 1 output v oh v ccif =5v 2.4 v12 logic 1 output current (int1 pin) i oh , int1 (v cc2 , v bat ) -0.3v -100 a v cc1 =2.0v 0.425 v cc1 active supply current i cc1a v cc1 =5v 1.28 ma 4, 9 v cc1 =2.0v 25.3 v cc1 timekeeping current i cc1t v cc1 =5v 81 a 3,9 v cc2 =2.0v 0.4 v cc2 active supply current i cc2a v cc2 =5v 1.2 ma 4, 10 v cc2 =2.0v 0.4 v cc2 timekeeping current i cc2t v cc2 =5v 1 a 3, 10 *unless otherwise noted.
ds1306 13 of 17 dc electrical characteristics (cont?d) (0 c to 70 c or ?40c to +85c; v cc = 2.0 to 5.5v*) parameter symbol min typ max units notes battery timekeeping current i batt v bat =3v 550 na 12 battery timekeeping current (ind) i batt v bat =3v 800 na 12 trickle charge resistors r1 r2 r3 2 4 8 k ? k ? k ? trickle charger diode voltage drop v td 0.7 v capacitance (t a = 25 c) parameter symbol condition typ max units notes input capacitance c i 10 pf output capacitance c o 15 pf crystal capacitance c x 6pf 3-wire ac electrical characteristics (0 c to 70 c or ?40c to +85c; v cc = 2.0v to 5.5v*) parameter symbol min typ max units notes v cc =2.0v 200 data to clk setup t dc v cc =5v 50 ns 5, 6 v cc =2.0v 280 clk to data hold t cdh v cc =5v 70 ns 5, 6 v cc =2.0v 800 clk to data delay t cdd v cc =5v 200 ns 5, 6, 7 v cc =2.0v 1000 clk low time t cl v cc =5v 250 ns 6 v cc =2.0v 1000 clk high time t ch v cc =5v 250 ns 6 v cc =2.0v 0.6 clk frequency t clk v cc =5v dc 2.0 mhz 6 v cc =2.0v 2000 clk rise and fall t r , t f v cc =5v 500 ns v cc =2.0v 4 ce to clk setup t cc v cc =5v 1 s 6 v cc =2.0v 240 clk to ce hold t cch v cc =5v 60 ns 6 v cc =2.0v 4 ce inactive time t cwh v cc =5v 1 s 6 v cc =2.0v 280 ce to output high z t cdz v cc =5v 70 ns 5, 6 v cc =2.0v 280 sclk to output high z t ccz v cc =5v 70 ns 5, 6 *unless otherwise noted.
ds1306 14 of 17 timing diagram: 3-wire read data transfer figure 10 timing diagram: 3-wire write data transfer figure 11
ds1306 15 of 17 spi ac electrical characteristics (0 c to 70 c or ?40c to +85c; v cc = 2.0 to 5.5v*) parameter symbol min typ max units notes v cc =2.0v 200 data to clk setup t dc v cc =5v 50 ns 5, 6 v cc =2.0v 280 clk to data hold t cdh v cc =5v 70 ns 5, 6 v cc =2.0v 800 clk to data delay t cdd v cc =5v 200 ns 5, 6, 7 v cc =2.0v 1000 clk low time t cl v cc =5v 250 ns 6 v cc =2.0v 1000 clk high time t ch v cc =5v 250 ns 6 v cc =2.0v 0.6 clk frequency t clk v cc =5v dc 2.0 mhz 6 v cc =2.0v 2000 clk rise and fall t r , t f v cc =5v 500 ns v cc =2.0v 4 ce to clk setup t cc v cc =5v 1 s 6 v cc =2.0v 240 clk to ce hold t cch v cc =5v 60 ns 6 v cc =2.0v 4 ce inactive time t cwh v cc =5v 1 s 6 v cc =2.0v 280 ce to output high z t cdz v cc =5v 70 ns 5, 6 *unless otherwise noted.
ds1306 16 of 17 timing diagram: spi read data transfer figure 12 timing diagram: spi write data transfer figure 13 sclk can be either polarity, timing shown for cpol = 1.
ds1306 17 of 17 notes: 1. all voltages are referenced to ground. 2. logic 0 voltages are specified at a sink current of 4 ma at v cc =5v and 1.5 ma at v cc =2.0v, v ol =gnd for capacitive loads. 3. i cc1t and i cc2t are specified with ce set to a logic 0. 4. i cc1a and i cc2a are specified with ce= v cc , sclk=2 mhz (0-v cc ) at v cc =5v; sclk=500 khz (0-v cc ) at v cc =2.0v. 5. measured at v ih =2.0v or v il =0.8v and 10 ms maximum rise and fall time. 6. measured with 50 pf load. 7. measured at v oh =2.4v or v ol =0.4v. 8. v cc =v cc1 , when v cc1 >v cc2 +0.2v (typical); v cc =v cc2 , when v cc2 >v cc1 . 9. v cc2 =0v. 10. v cc1 =0v. 11. v cc1

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